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package: 8-pin tssop (suffix le) the a1454 linear hall effect sensor ic provides a 12-bit digital output word that is proportional to the strength of the magnetic field that is present. its quiescent output value is at mid-scale, and it comes in 2 different factory programmed sensitivity ranges: 2lsb/g & 4lsb/g. the sensitivity temperature coefficient is also factory programmed to support either neodymium or ferrite magnets. the a1454 incorporates an i 2 c interface for easy integration into a wide variety of applications. the i 2 c address can either be set by external resistors or programmed via eeprom, to support up to 127 unique i 2 c addresses, allowing for multiple ics on the same bus. it also includes 16 bytes of user programmable eeprom. the a1454 i 2 c interface provides a user-controlled sleep input command that puts the device in micro-power mode, which reduces the current consumption of the a1454. this low power feature makes the a1454 perfect for portable, battery-operated applications. the bicmos monolithic process allows the integration of both high precision analog and high-density digital circuitry. the a1454 integrates the hall element, a 12-bit adc, gain & offset compensation circuitry, eeprom memory and the i 2 c interface on a single monolithic ic that is packaged in a space saving surface mount package. a1454-ds ? 1 mm thin (tssop-08) package ? 2 factory programmed sensitivity options: 2 lsb/g (for fields up to 1000 g) and 4 lsb/g (500 g) ? temperature-stable sensitivity for ndfeb and ferrite magnets ? i 2 c interface for easy integration with support for up to 127 unique addresses ? eeprom stores factory programmed settings and up to 16 bytes of user information (programmable through the i 2 c interface) ? micro-power sleep mode through i 2 c command for minimizing power in battery-operated applications ? precise recoverability after temperature cycling ? wide ambient temperature range: C40c to 125c ? 12-bit adc with 10-bit enob (effective number of bits) 3v hall effect linear sensor with i 2 c output functional block diagram not to scale a1454 vcc sleep mode i c serial 2 interface hall element adc digital controller eeprom memory charge pump gnd slave address adc sda scl adr0 adr1 features and benefits description typical application circuit vcc vcc vcc vcc vcc vcc gnd nc nc sda a1454 scl adr1 adr0 0.1 f v a0 10 k 10 k i c 2 master v a1 engineering samples are available on a limited basis. contact your sales or applications support office for additional information.
2 package le, 8-pin tssop pin-out diagram absolute maximum ratings characteristic symbol notes rating unit forward supply voltage v cc 5.0 v reverse supply voltage v rcc C0.1 v forward scl pin voltage v i2c(scl) 5.5 v forward sda pin voltage v i2c(sda) 5.5 v reverse scl and sda voltage v ri2c C0.1 v operating ambient temperature t a range k C40 to 125 oc maximum junction temperature t j (max) 165 oc storage temperature 1 t stg C65 to 170 oc 1 stresses beyond the absolute maximum ratings may result in permanent device damage. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. terminal list table number name function 1 vcc device supply voltage pin 2 adr0 address select pin 0 3 gnd device ground pin 4 nc no connection 5 nc no connection 6 adr1 address select pin1 7 sda i 2 c interface sda pin 8 scl i 2 c interface scl pin selection guide part number sensitivity target magnet packing package a1454kletr-2f-t 2 lsb/g ferrite 4000 pieces per reel 8-pin tssop package a1454kletr-4f-t 4 lsb/g ferrite A1454KLETR-2N-T 2 lsb/g neodymium a1454kletr-4n-t 4 lsb/g neodymium *contact allegro ? for additional packing options. vcc adr0 gnd scl sda adr1 nc nc 1 2 3 4 5 6 7 8 specifications thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance r ja on single-layer pcb with copper limited to solder pads 137 oc/w *additional thermal information available on the allegro website. pin-out diagram and terminal list table 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
3 characteristics symbol test conditions min. typ. max. unit electrical characteristics supply voltage v cc normal operation 2.65 3.0 3.5 v eeprom programming 2.8 3 C 3.5 v turn on delay 1 t don after v cc(min) is reached C 30 C ms supply current i cc v cc = v cc(max) , active mode C 2 5 ma v cc = v cc(max) , sleep mode C 0.2 1 a v cc = v cc(max) , eeprom programming occurring C 2 5 ma internal bandwidth 2 bw i small signal C3 db C 2 C khz output refresh rate 3 f out C 32 C khz por v cc low time 4 t por v cc goes below v cc(min) C 100 C ms number of eeprom writes C number of times the eeprom can be written C C 1000 writes address pin characteristics address value 0 reference 5 v addr0 adr0, adr1 pins C 0 0.1 x vcc address value 1 reference 5 v addr1 adr0, adr1 pins 0.23 0.33 0.43 x vcc address value 2 reference 5 v addr2 adr0, adr1 pins 0.57 0.67 0.77 x vcc address value 3 reference 5 v addr3 adr0, adr1 pins 0.90 0.100 C x vcc address pin input resistance r in adr0, adr1 pins 0.8 1 1.2 m 1 the device will not respond to i 2 c inputs until after the turn-on delay. 2 determined by design and characterization, not evaluated at final test. 3 the rate at which a new output value is available to be read by the i 2 c interface. 4 if v cc is below v cc(min) for this amount of time, the device will reset when v cc goes above v cc(min) . if the device is in sleep mode when v cc goes below v cc(min) , this time will be much longer due to the slow discharge of internal capacitors while in sleep mode. 5 based on design simulation and device characterization. not verified for each part at final test. operating characteristics : valid at t a = 25c, v cc = 3.0 v, and c bypass = 0.1 f; unless otherwise noted 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
4 characteristics symbol test conditions min. typ. max. unit 1 factory programmed quiescent voltage output qvo a1454kletr-4n,t a = 25c C 10 C lsb a1454kletr-4f,t a = 25c C 10 C lsb a1454kletr-2n,t a = 25c C 10 C lsb a1454kletr-2f,t a = 25c C 10 C lsb factory programmed sensitivity sens a1454kletr-4n,t a = 25c fsi = +/- 500 g C 4.0 C lsb/g a1454kletr-4f,t a = 25c fsi = +/- 500 g C 4.0 C lsb/g a1454kletr-2n,t a = 25c fsi = +/- 1000 g C 2.0 C lsb/g a1454kletr-2f,t a = 25c fsi = +/- 1000 g C 2.0 C lsb/g sensitivity temperature coefficient tc sens ndfeb compensated 2 applies to part numbers with suffix n C 0.12 C %/oc ferrite compensated 3 applies to part numbers with suffix f C 0.21 C %/oc linearity sensitivity error 4 lin err C <1 C % effective number of bits field = 1000 g, temp = 25oc, bw = 2 khz. C ~10 C bits effective number of bits field = 500 g, temp = 25Cc, bw = 2 khz. C ~9 C bits sensitivity error vs. temp sens err C40oc ~ +85oc C <3 C % C40oc ~ +125oc C <6 C % 1 1 g (gauss) = 0.1 mt (millitesla). 2 the slope of the hall gain function with temperature change is meant to compensate for the variation of a neodymium magnet with temperature. 3 the slope of the hall gain function with temperature change is meant to compensate for the variation of a ferrite magnet with temperature. 4 see characteristic definitions section. magnetic calibration characteristics : valid at t a = 25c and c bypass = 0.1 f; unless otherwise noted 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
5 characteristics symbol test conditions min. typ. max. unit bus free time between stop and start t buf 1.3 C C s hold time start condition t ndsta 0.6 C C s setup time for repeated start condition t susta 0.6 C C s scl low time t low 1.3 C C s scl high time t high 0.6 C C s data setup time t sudat 100 C C ns data hold time t hddat 0 C 900 ns setup time for stop condition t susto 0.6 C C s logic input low level (sda, scl pins) v il C C 30 %v cc logic input high level (sda, scl pins) v ih 70 C C %v cc logic input current i in v in = 0 v to v cc C1 0 1 a output voltage (sda pin) v ol i load = 1.5 ma C C 0.36 v clock frequency (scl pin) f clk C C 400 khz output fall time (sda pin) t f r pu = 2.4 k, c b = 100 pf C C 250 ns i 2 c pull-up resistance r ext 2.4 10 C k total capacitive load for each of sda and scl buses c b C C 100 pf *these values are ratiometric to the supply voltage. i 2 c interface characteristics are ensured by design and not factory tested. *contact allegro for 1.8v i 2 c bus support. i 2 c interface characteristics* : valid at t a = 25c, v cc = 3.0 v, and rext = 10 k; unless otherwise noted t sust a t suda t t low t sust o t hdst a t hdda t t high t buf sda scl figure 1: i 2 c interface timing diagram 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
6 primary registers customer accessible registers the following table shows registers that are customer accessible and can be read/written using the i 2 c protocol. table 1: customer accessible registers address name bit field 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x1d temp out [11:0] temperature sensor output 0x1f output [11:0] sensor output 0x20 sleep [)] sleep sensor output the a1454 provides a 12 bit digital output that is proportional to the magnetic field applied normally to the hall element. table 2: output [11:0], address 0x1f, bit defnition table bits address name value description r/w default 11:0 0x1f output 0/1 (for each bit) 12-bit signed signal proportional to field strength intensity. 0g is denoted by 12b0 value. r C temperature sensor output the a1454 provides a 12-bit digital output that is proportional to the junction temperature of the hall-sensor ic. table 3: temp out [11:0], address 0x1d, bit defnition table bits address name value description r/w default 11:0 0x1d temp out 0/1 (for each bit) 12-bit signed signal proportional to temperature. 25c is denoted by a 12b0 value. temperature slope is ~ 8 lsb/oc. r C table 4: sleep [0], address 0x20, bit defnition table bits address name value description r/w default 0 0x20 sleep mode 0/1 sleep mode enable bit r/w C sleep mode the 1454 supports a sleep mode where numerous sub-systems are powered. to enter sleep mode, the user sets the sleep con - trol bit. to awake from sleep mode the user clears the sleep bit. since the i2c logic uses scl as its clock source and the sleep bit implemented in the scl clock domain, the system clock does not need to be operational for the sleep output to be cleared. within a period of about 50 s after clearing the sleep bit, the system clock will be operational, and the a1454 ic will respond to i 2 c commands. furthermore, within a period of about 150 s after clearing the sleep bit, the a1454 will be able to provide a digital output that is fairly accurate, but not temperature compensated. lastly, within a period of about 500 s after clearing the sleep bit, the a1454 will be able to provide an output value that is accurate to within the device accuracy specifications. therefore, a design trade-off can be made between wake-up time, and accuracy of output, based on the specific system-level requirements. 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
7 characteristic definitions active mode response time the active mode response time, t pactive , is the time required to settle internal voltages with an applied magnetic field, after either v cc is above v cc(min) , or the command to activate from sleep mode has been received. the i 2 c master can issue a com- mand to activate the device from sleep mode by clearing the sleep bit (cr 0x04, d0). after the sleep bit has been cleared, the device requires a finite time to power-on its internal compo- nents before accurately responding to an applied magnetic field. (note: when coming out of sleep mode, the ic acts as if it is being powered on. this means that all volatile registers are reset to their default values, and those registers which can be pro- grammed into eeprom are reloaded with what is in eeprom.) maximum applied field the a1454 device will be able to handle magnetic signals as large as b max before internal amplifiers begin to saturate. fields above these values will result in uncertain device operation out- side specification limits. linear sensitivity error the a1454 is designed to provide a linear output in response to a ramping applied magnetic field. consider two magnetic fields, b1 and b2. ideally, the sensitivity of a device is the same for both fields, for a given supply voltage and temperature. linearity error is present when there is a difference between the sensitivities measured at b1 and b2. linearity error is calculated separately for the positive (l iner- rpos ) and negative (l inerrneg ) applied magnetic fields. linearity error (%) is measured and defined as: lin = errpos 1? sens bpos2 sens bpos1 100 (%) 100 (%) lin = errneg 1? sens bneg2 sens bneg1 ( ( ) ) where: sens bx = |v ?v | out(bx) out(q) b x and b posx and b negx are positive and negative magnetic fields, with respect to the quiescent voltage output such that |b pos2 | = 2 |b pos1 | and |b neg2 | = 2 |b neg1 |. in the above equation, v out(q) is the quiescent voltage output, and v out(bx) is the hall voltage when the field, b x , is applied. then: lin err errpos errneg = max(lin , lin ) i 2 c interface this is a serial interface that uses two bus lines, scl and sda, to access the internal control registers. data is exchanged between a microcontroller (master) and the a1454 (slave). the clock input to scl is generated by the master, while the sda line functions as either an input or an open drain output, depending on the direc- tion of the data. the i 2 c input thresholds depend on the v cc voltage of the a1454. the threshold levels over the operating v cc range are compatible with 3 v logic. timing considerations i 2 c communication is composed of several steps in the following sequence: 1. start condition. defined by a negative edge on the sda line, while scl is high. 2. address cycle. 7 bits of address, plus 1 bit to indicate write (0) or read (1), and an acknowledge bit. 3. data cycles. reading or writing 8 bits of data followed by an acknowledge bit. 4. stop condition. defined by a positive edge on the sda line, while scl is high. except to indicate a start or stop condition, sda must be stable while the clock is high. sda can only be changed while scl is low. it is possible for the start or stop condition to occur at any time during a data transfer. the a1454 always responds by reset- ting the data transfer sequence. the state of the read/ write bit is set to 0 to indicate a write cycle and set to 1 to indicate a read cycle. the master monitors for an acknowledge pulse to determine if the slave device is responding to the address byte sent to the a1454. when the a1454 decodes the 7-bit address field as a valid address, it responds by pulling sda low during the ninth clock cycle. during a data write from the master, the a1454 pulls sda low during the clock cycle that follows the data byte, in order to indi- cate that the data has been successfully received. after sending either an address byte or a data byte, the master device must release the sda line before the ninth clock cycle, in order to allow the handshaking to occur. 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
8 i 2 c command to write to the a1454 the master controls the a1454 by programming it as a slave. to do so, the master transmits data bits to the sda input of the a1454, in synchronization with the clocking signal the master transmits simultaneously on the scl input. a complete transmission begins with the master pulling sda low (start bit), and completes with the master releasing the sda line (stop bit). as shown in figure 1, between these points, the master transmits two address bytes, the first with the a1454 (chip) address bits and a write command bit (d0 = 0) and the second with the initial target register address, which are followed by the data bytes. after every byte, regardless of byte payload, the slave a1454 acknowledges by transmitting a low to the master on the sda line. multiple data bytes can be written by one i 2 c sequence, as shown in figure 2. after the slave acknowledges a data byte, instead of sending a stop bit, the master sends the next data byte. only after the final data byte is written and the slave acknowledges, does the master provide a stop bit. the a1454 automatically directs each additional data byte to the next register, in order of regiter address number. note that only the initial register address is required. this allows faster data entry, although it restricts data entry to sequential registers. if non-sequential registers are to be written, separate write commands can be sent. a1454 (slave) acknowledge a1454 (slave) acknowledge a1454 (slave) acknowledge a1454 (slave) acknowledge a1454 (slave) acknowledge a1454 (slave) acknowledge w rite bit w rite bit slave address slave data1 start register address register data2 register data 0 register data 3 sda sda scl scl d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 d0 w ak ak d7 d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 d0 ak ak d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 d0 ak ak stop . . . . . . . . . . . . 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7 7 7 8 8 8 8 8 8 9 9 9 9 9 9 figure 2: i 2 c write operation customer write access before attempting to write to any of the serial registers or eeprom memory locations in the a1454, an access code must be entered, to put the device in customer access mode. if cus - tomer access mode is configured, then no writes to the device are allowed. the only exception this this is the sleep bit, which can be written regardless of the access mode. furthermore, any register or eeprom location can be read at any time regardless of the access mode. to enter either customer access mode, an access command needs to be sent via the i 2 c interface. the command is simply a serial write operation with the address and data values as shown in table 2. once the access mode is set, it is not possible to change the mode without power-cycling the device. there is no time limit for entering the code. table 5: customer access code address data customer access mode 0x24 0x2c413534 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
9 i 2 c command to read from the a1454 this section applies to the reading of both volatile and non- volatile eeprom registers. the master can read back the register values from the a1454. similar to writing, the master transmits data bits to the sda input of the a1454, in synchronization with the clocking signal the master transmits simultaneously on the scl input. a complete transmission consists of a read command from the master and a response from the a1454. it begins with the master pulling sda low (start bit), and completes with the master releasing the sda line (stop bit). as shown in figure 3, between these points, the master transmits two address bytes, the first with the a1454 (chip) address bits and a write command bit (d0 = 0) and the second with the initial source register address. after each address byte, the slave a1454 acknowledges by transmitting a low to the master on the sda line. the master then issues another start bit (referred to as restart ) followed by the same slave chip address and the read/ write bit set to read (d0 = 1). the a1454 then provides the data byte from the addressed regiter, synchronized with the clock pulse supplied by the master (the master must provide the clock pulses, as the a1454 slave does not have the capability to generate them). in figure 3, the transmission is of the entire contents of a single register location (bits 31:0). optionally, the i2c master can continue to acknowledge instead of issuing a nack and stop - ping. this will result in the transfer of data [31:24] from reg address+1. the master can then continue acknowledging or issue the not acknowledge/stop after any byte to stop receiving data. note that only the initial register address is required. this allows faster data retrieval, although it restricts data retrieval to sequen - tial registers. when the master provides non-acknowledge bit and stop bit, the a1454 stops sending data. if non-sequential registers are to be read, separate read commands can be sent. . . . . . . 1 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 9 9 9 9 1 a1454 (slave) acknowledge a1454 (slave) acknowledge a1454 (slave) acknowledge a1454 (slave) acknowledge w rite bit read bit master restart slave address slave address start sda sda scl scl register address register data d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 d0 ak ak 11 1 22 2 33 3 44 4 55 5 66 6 77 7 88 8 99 9 a1454 (slave) acknowledge a1454 (slave) acknowledge master non?acknowledge register data1 register data2 register data3 sda scl stop d7 d7 d7 d6 d6 d6 d5 d5 d5 d4 d4 d4 d3 d3 d3 d2 d2 d2 d1 d1 d1 d0 d0 d0 ak ak nak d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 d0 ak ak . . . . . . figure 3: i 2 c read operation 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
10 figure 4: programming eeprom blocks this sequence enables programming of eeprom blocks 2 through 3 from the volatile registers which shadow those blocks. a1454 (slave) acknowledge a1454 (slave) acknowledge a1454 (slave) acknowledge a1454 (slave) acknowledge a1454 (slave) acknowledge a1454 (slave) acknowledge w rite bit slave address start eeprom register address eeprom w rite data0 eeprom w rite data3 eeprom w rite data2 eeprom w rite data1 sda sda scl scl w w d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 d0 ak ak d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 d0 ak ak d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 d0 ak ak stop . . . . . . . . . . . . 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7 7 7 8 8 8 8 8 8 9 9 9 9 9 9 i 2 c address for the a1454 the default device address, in the case where va0 and va1 are set to vcc, is given by binary 1101 111[0/1], where the last bit determines if it is a read or a write instruction. for more options on slave addressing for the a1454, refer to the section: i 2 c device (slave) address coding. eeprom functionality the on-chip eeprom is divided into eight rows, each thirty two bits long, with six of the msbs being used for eeprom ecc. on power-up, all registers in eeprom address 0x03 to 0x07 are loaded into the volatile registers which shadow them. for example, ee address 0x03 is loaded into registers 0x0c. the user can overwrite these volatile registers, and they will be reset to the values in the eeprom only on a power cycle of the ic. programming eeprom blocks programming of the eeprom is done through the i 2 c interface. each row of eeprom can only be written 1000 times. the i 2 c command for writing to eeprom is very similar to the general i 2 c command for writing to the volatile serial registers in the a1454. before attempting to write to eeprom, please ensure that the device is in customer access mode. for more details see the customer write access section on page 7. a complete transmission begins with the master pulling sda low (start bit), and completes with the master releasing the sda line (stop bit). as shown in figure 4, between these points, the master transmits two address bytes, the first with the a1454 (chip) address bits and a write command bit (d0 = 0) and the sec - ond with the initial target eeprom register address, which are followed by the data bytes. after every byte, regardless of byte payload, the slave a1454 acknowledges by transmitting a low to the master on the sda line. the 1454 always writes one entire eeprom row at a time. as shown in figure 4. after the slave acknowledges a data byte, the master sends the next data byte. only after the final data byte is written and the slave acknowledges, does the master provide a stop bit. the a1454 now takes these 4 data bytes and writes them to the requested register address. it takes the eeprom 30 ms to perform the write command. after such time, the host can issue the next i 2 c eeprom write command, if desired. 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
11 eeprom memory check the eeprom memory check provides the capability to vary the eeprom reference voltages and compare the data from each reference voltage, to ensure that no eeprom memory cells are corrupted. a high reference voltage is used ensure that 1s are correctly programmed and a low reference voltage is used to ensure that the 0s are correctly programmed. the tables 6 and 7 describe the features available in customer accessible register eeprom check. table 6: customer accessible register eeprom check register name register address bit number 25:6 eeprom check 0x1c unused mm ms 0 0 mci table 7: customer accessible register eeprom check parameter name description value mci: memory check initiate the mci bit can be written by the customer to initiate an eeprom memory check procedure. this bit will self-clear upon completion of the memory test. 0: reset condition 1: start memory check bit 1 must be set to 0 0 bit 2 must be set to 0 0 ms[1:0]: memory status these are status bits that provide information on the progress and result of the memory check. these bits are cleared after a read, or a system reset. 00: reset condition 01: pass - no failure detected. 10: fail C failure detected 11: running - memory check ongoing. mm in the case of ms [1:0] = [10], i.e. failure detected, mm will provide additional diagnostic information, indicating whether the failing memory reference was the low reference, or the high reference. 0: low reference failed 1: high reference failed 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
12 i 2 c device (slave) address coding the four lsbs of the device (slave) address (a3, a2, a1, and a0) can be set by applying different voltages to pins adr0 and adr1 as show in figure x and defined in table x. table 1: a1454 i 2 c address bits address bit a6 a5 a4 a3 a2 a1 a0 binary device address value 0/1 0/1 0/1 0/1 0/1 0/1 0/1 table 2: slave address decoding voltage on ad1 pin, v a1 ( vcc ) voltage on ad0 pin, v a0 ( vcc ) 4-bit code from adr0 and adr1 voltages slave address bits slave address e3 e2 e1 e0 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 0 1 1 0 0 0 0 0 96 0.33 0 0 0 1 1 1 0 0 0 0 1 97 0.67 0 0 1 0 1 1 0 0 0 1 0 98 1 0 0 1 1 1 1 0 0 0 1 1 99 0.33 0 0 1 0 0 1 1 0 0 1 0 0 100 0.33 0 1 0 1 1 1 0 0 1 0 1 101 0.67 0 1 1 0 1 1 0 0 1 1 0 102 1 0 1 1 1 1 1 0 0 1 1 1 103 0.67 0 1 0 0 0 1 1 0 1 0 0 0 104 0.33 1 0 0 1 1 1 0 1 0 0 1 105 0.67 1 0 1 0 1 1 0 1 0 1 0 106 1 1 0 1 1 1 1 0 1 0 1 1 107 1 0 1 1 0 0 1 1 0 1 1 0 0 108 0.33 1 1 1 0 1 1 0 1 1 1 0 109 0.67 1 1 1 0 1 1 0 1 1 1 0 110 1 1 1 1 1 x x x x x x x programmable: 0-127, (using 7-bit eeprom field). set at factory for default = 111 note: different values for the three msbs of the address (a6, a5, and a4) are available for factory programming if a conflict with other units occurs in the application design. 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
13 eeprom customer space register 0x02 (bits 25:0) are available as customer eeprom space. this memory location is intended to be utilized by the user for storing information, such as factory time stamps, lot numbers, version numbers, and so forth. this registers is not shadowed, and so must be written 4 bytes at a time, as described in the programming eeprom section (second method). also, as with all the eeprom registers, these registers can only be written to 1000 times. table 3: eeprom memory map adr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 auto ecc bits factory access only 0x01 auto ecc bits factory access only 0x02 auto ecc bits customer id 0x03 auto ecc bits test_field_tbd cust_slave_address 0x04 auto ecc bits factory locked 0x05 auto ecc bits factory locked 0x06 auto ecc bits factory locked 0x07 auto ecc bits factory locked table 4: volatile register that shadow eeprom (registers are loaded from eeprom on power-up) adr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0b auto ecc bits test_field_tbd cust_slave_address 0x0c auto ecc bits factory locked 0x0d auto ecc bits factory locked 0x0e auto ecc bits factory locked 0x0f auto ecc bits factory locked 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
14 for reference only ? not for t ooling use (reference mo-153 aa) dimensions in millimeters - not to scale dimensions exclusive of mol d? ash, gate burrs, and dambar protrusions exact case and lead con?guration at supplier discretion within limits shown 6.40 bsc 1.70 b b c c e d 12 8 pcb layout reference v iew standard branding reference v iew 1 nnn yyww a = last 3 digits of device part number = supplier emblem = last two digits of year of manufactur e = w eek of manufactur e n y w te rminal #1 mark area reference land pattern layout (reference ipc7351 sop65p640x1 10-8m); all pads minimum of 0.20 mm from all adjacent pads; adjust as necessar y to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias can improve thermal dissipatio n (reference eia/jedec standard jesd51-5) branding scale and appearance at supplier discretio n hall element, not to scal e activea rea depth = 0.36 mm ref 3.00 0.10 1.50 6.40 bsc 4.40 0.10 2.20 d d e d 12 8 branded face 8x 0.10 c 0.30 0.19 0.65 bsc 0.25 bsc 0.15 0.05 1.10 max sea ting plane c 8o 0o 0.02 0.09 0.60 1.00 ref +0.15 -0.10 sea ting plane gauge plane a figure 5: package le, 8-pin tssop package outline diagram 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
15 revision history revision current revision date description of revision C april 3, 2015 initial release copyright ?2014-15, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com 3v hall effect linear sensor with i 2 c output a1454 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com

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